The present invention relates generally to manufacturing substrates. More particularly, the invention provides a method and device for improved semiconductor substrates to form advanced semiconductor devices. Merely by way of example, the invention has been applied to a metallic substrate that includes a plurality of panels and/or tiles, which are bonded on the substrate, for the manufacture of the advanced semiconductor devices. But it would be recognized that the invention has a much broader range of applicability.
As technology progresses, semiconductor manufacturers have continually strived to use ever larger wafers to obtain economies of scale, and consequently lower the cost of individual semiconductor devices. Commonly, silicon crystal boules can be readily grown large enough to slice into 12 inch diameter wafers. The 12 inch wafers have been produced for single crystal silicon materials for a variety of applications. Although the single crystal silicon has many benefits, there are still numerous disadvantages.
Many conventional industries have been increasingly reliant on compound semiconductor devices fabricated from compound semiconductors such as gallium arsenide, indium phosphide, and gallium nitride. Unfortunately, integrated circuits made from these semiconducting compounds are still relatively expensive compared to circuits made from silicon semiconductors. This cost difference is largely attributable to the respective material costs, and wafer processing costs. Other limitations also exist with compound semiconductor materials.
Compound semiconductor wafers are more prone to damage. For example, they are more brittle than conventional single crystal silicon wafers. Growing large crystal boules of compound semiconductor material is extremely difficult compared with growing large single crystal silicon boules. The maximum diameters for commercially-produced compound semiconductor wafers of gallium arsenide, indium phosphide and gallium nitride are respectively six inches, four inches and two inches in conventional commercial applications.
Larger compound semiconductor wafers would be desirable. Unfortunately, larger diameter wafers are difficult to make efficiently. Even if larger boules of compound semiconductor material could be produced, handling the resulting large-diameter compound semiconductor wafers would generally be problematic. Compound semiconductor wafers of the desired thickness and diameter would be extremely fragile and prone to breakage. Here, the larger wafers would generally break due to the brittle nature of these semiconductor compounds. Accordingly, certain techniques have been proposed to manufacture larger compound semiconductor wafers using an epitaxial grown layer.
As merely an example, a conventional process for fabricating compound semiconductor chips could be outlined in steps (i) to (vii) listed below.
(i) Grow epitaxial device layers on mono-crystalline substrate.
(ii) Pattern these epitaxial layers and other deposited dielectric and metallic layers using photolithographic techniques.
(iii) Bond wafers face-down to a temporary supporting substrate after front-side process is complete.
(iv) Thin wafers by mechanical grinding or lapping back-side.
(v) Create “via holes” in the substrate, which provide a means for connecting the back-side ground to appropriate front-side ground connections.
(vi) Deposit a metal film on the wafer's back-side to provide a ground plane, and coat the walls of the via holes, thereby making contact with the front-side ground connections.
(vii) Dice wafer into individual chips.
In the above conventional process, wafers are typically 625 μm in thickness during steps (i), (ii) and (iii), and have sufficient mechanical strength to avoid breakage with careful handling. Wafers are typically thinned to around 50 to 100 μm in thickness in step (iv). Thinning wafers has numerous advantages, which relate to:                (i) reducing the depth (and also the size) of via holes, as well as parasitic inductance associated with the via holes;        (ii) conducting heat away from front-side devices towards the back-side, which is normally attached to a heat sink; and        (iii) preventing electromagnetic resonance in the substrate at high frequencies.        
Handling thinned compound semiconductor wafers is often difficult, and compound semiconductor wafers are commonly broken from step (iv) onwards. Breakage is costly, since most of the processing (steps (i) to (iii)) is already complete. The fragility of compound semiconductor materials also causes breakages of resulting chip devices, and restricts the larger size of practical chip designs that use compound semiconductor materials. Here, larger sized compound semiconductor materials are not practical to make efficiently.
In conventional compound semiconductor wafer processing, via holes are also required to connect certain grounded circuit elements on the front side of the wafer to the ground plane on the back side. Typically these via holes are etched from the back side of the wafer towards the front side elements. Certain limitations exist with processing of via holes for compound semiconductor wafers. Difficulties often arise because of a need to align features on one side of the wafer with corresponding features on the other side of the wafer. Alignment tolerances of these via hole features are therefore poor. Additionally, there is often a restriction on the number and shape of via holes because they reduce the mechanical strength of the wafer. These and other limitations have been described throughout the present specification and more particularly below.
In view of the above, a need exists for improved techniques for producing and handling semiconductor wafers. In particular, a need exists for techniques suitable for assisting practical and cost-effective production of compound semiconductor devices.